1. Field of the Invention
The present invention relates to logic simulation and in particular to an integrated logic simulator including a serial simulation engine and a concurrent simulation engine.
2. Related Art
Logic simulation is an essential step in the design flow of electronic circuits. Logic simulation is usually performed with Electronic Design Automation (EDA) software tools referred to as logic simulators, which process hardware designs typically provided in the form of Hardware Description Language (HDL) code. Hardware designers perform extensive logic simulations to verify that a hardware design complies with its specifications, before committing the hardware design to the physical implementation phase that produces the actual electronic circuit. In a typical hardware design flow, a functional verification process is carried out along with the design process in order to minimize the risk of producing a circuit that is not compliant with its specifications. A logic simulation typically generates as its results the waveforms of a set of circuit signals the user is interested in observing. The user can analyze and visualize the generated waveforms to verify that the hardware design operates correctly. Logic simulators also support simulating hardware designs with embedded assertions, which use the values of the circuit signals to detect conditions resulting in circuit malfunctioning. A logic simulator evaluates such assertions while simulating the circuit, and reports their violations to the user. Based on these violation reports, the user can uncover and fix design errors in the hardware design.